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<h4 class="subsection" id="LoongArch-Options-1"><span>3.19.22 LoongArch Options<a class="copiable-link" href="#LoongArch-Options-1"> &para;</a></span></h4>
<a class="index-entry-id" id="index-LoongArch-Options"></a>

<p>These command-line options are defined for LoongArch targets:
</p>
<dl class="table">
<dt><a id="index-march-7"></a><span><code class="code">-march=<var class="var">cpu-type</var></code><a class="copiable-link" href="#index-march-7"> &para;</a></span></dt>
<dd><p>Generate instructions for the machine type <var class="var">cpu-type</var>.  In contrast to
<samp class="option">-mtune=<var class="var">cpu-type</var></samp>, which merely tunes the generated code
for the specified <var class="var">cpu-type</var>, <samp class="option">-march=<var class="var">cpu-type</var></samp> allows GCC
to generate code that may not run at all on processors other than the one
indicated.  Specifying <samp class="option">-march=<var class="var">cpu-type</var></samp> implies
<samp class="option">-mtune=<var class="var">cpu-type</var></samp>, except where noted otherwise.
</p>
<p>The choices for <var class="var">cpu-type</var> are:
</p>
<dl class="table">
<dt>&lsquo;<samp class="samp">native</samp>&rsquo;</dt>
<dd><p>This selects the CPU to generate code for at compilation time by determining
the processor type of the compiling machine.  Using <samp class="option">-march=native</samp>
enables all instruction subsets supported by the local machine (hence
the result might not run on different machines).  Using <samp class="option">-mtune=native</samp>
produces code optimized for the local machine under the constraints
of the selected instruction set.
</p></dd>
<dt>&lsquo;<samp class="samp">loongarch64</samp>&rsquo;</dt>
<dd><p>A generic CPU with 64-bit extensions.
</p></dd>
<dt>&lsquo;<samp class="samp">la464</samp>&rsquo;</dt>
<dd><p>LoongArch LA464 CPU with LBT, LSX, LASX, LVZ.
</p></dd>
</dl>

</dd>
<dt><a id="index-mtune-8"></a><span><code class="code">-mtune=<var class="var">cpu-type</var></code><a class="copiable-link" href="#index-mtune-8"> &para;</a></span></dt>
<dd><p>Optimize the output for the given processor, specified by microarchitecture
name.
</p>
</dd>
<dt><a id="index-mabi-2"></a><span><code class="code">-mabi=<var class="var">base-abi-type</var></code><a class="copiable-link" href="#index-mabi-2"> &para;</a></span></dt>
<dd><p>Generate code for the specified calling convention.
<var class="var">base-abi-type</var> can be one of:
</p><dl class="table">
<dt>&lsquo;<samp class="samp">lp64d</samp>&rsquo;</dt>
<dd><p>Uses 64-bit general purpose registers and 32/64-bit floating-point
registers for parameter passing.  Data model is LP64, where &lsquo;<samp class="samp">int</samp>&rsquo;
is 32 bits, while &lsquo;<samp class="samp">long int</samp>&rsquo; and pointers are 64 bits.
</p></dd>
<dt>&lsquo;<samp class="samp">lp64f</samp>&rsquo;</dt>
<dd><p>Uses 64-bit general purpose registers and 32-bit floating-point
registers for parameter passing.  Data model is LP64, where &lsquo;<samp class="samp">int</samp>&rsquo;
is 32 bits, while &lsquo;<samp class="samp">long int</samp>&rsquo; and pointers are 64 bits.
</p></dd>
<dt>&lsquo;<samp class="samp">lp64s</samp>&rsquo;</dt>
<dd><p>Uses 64-bit general purpose registers and no floating-point
registers for parameter passing.  Data model is LP64, where &lsquo;<samp class="samp">int</samp>&rsquo;
is 32 bits, while &lsquo;<samp class="samp">long int</samp>&rsquo; and pointers are 64 bits.
</p></dd>
</dl>

</dd>
<dt><a id="index-mfpu-2"></a><span><code class="code">-mfpu=<var class="var">fpu-type</var></code><a class="copiable-link" href="#index-mfpu-2"> &para;</a></span></dt>
<dd><p>Generate code for the specified FPU type, which can be one of:
</p><dl class="table">
<dt>&lsquo;<samp class="samp">64</samp>&rsquo;</dt>
<dd><p>Allow the use of hardware floating-point instructions for 32-bit
and 64-bit operations.
</p></dd>
<dt>&lsquo;<samp class="samp">32</samp>&rsquo;</dt>
<dd><p>Allow the use of hardware floating-point instructions for 32-bit
operations.
</p></dd>
<dt>&lsquo;<samp class="samp">none</samp>&rsquo;</dt>
<dt>&lsquo;<samp class="samp">0</samp>&rsquo;</dt>
<dd><p>Prevent the use of hardware floating-point instructions.
</p></dd>
</dl>

</dd>
<dt><a id="index-msoft_002dfloat-5"></a><span><code class="code">-msoft-float</code><a class="copiable-link" href="#index-msoft_002dfloat-5"> &para;</a></span></dt>
<dd><p>Force <samp class="option">-mfpu=none</samp> and prevents the use of floating-point
registers for parameter passing.  This option may change the target
ABI.
</p>
</dd>
<dt><a id="index-msingle_002dfloat"></a><span><code class="code">-msingle-float</code><a class="copiable-link" href="#index-msingle_002dfloat"> &para;</a></span></dt>
<dd><p>Force <samp class="option">-mfpu=32</samp> and allow the use of 32-bit floating-point
registers for parameter passing.  This option may change the target
ABI.
</p>
</dd>
<dt><a id="index-mdouble_002dfloat-1"></a><span><code class="code">-mdouble-float</code><a class="copiable-link" href="#index-mdouble_002dfloat-1"> &para;</a></span></dt>
<dd><p>Force <samp class="option">-mfpu=64</samp> and allow the use of 32/64-bit floating-point
registers for parameter passing.  This option may change the target
ABI.
</p>
</dd>
<dt><a id="index-mbranch_002dcost-2"></a><span><code class="code">-mbranch-cost=<var class="var">n</var></code><a class="copiable-link" href="#index-mbranch_002dcost-2"> &para;</a></span></dt>
<dd><p>Set the cost of branches to roughly <var class="var">n</var> instructions.
</p>
</dd>
<dt><a id="index-mcheck_002dzero_002ddivision"></a><span><code class="code">-mcheck-zero-division</code><a class="copiable-link" href="#index-mcheck_002dzero_002ddivision"> &para;</a></span></dt>
<dt><code class="code">-mno-check-zero-divison</code></dt>
<dd><p>Trap (do not trap) on integer division by zero.  The default is
<samp class="option">-mcheck-zero-division</samp> for <samp class="option">-O0</samp> or <samp class="option">-Og</samp>, and
<samp class="option">-mno-check-zero-division</samp> for other optimization levels.
</p>
</dd>
<dt><a id="index-mcond_002dmove_002dint"></a><span><code class="code">-mcond-move-int</code><a class="copiable-link" href="#index-mcond_002dmove_002dint"> &para;</a></span></dt>
<dt><code class="code">-mno-cond-move-int</code></dt>
<dd><p>Conditional moves for integral data in general-purpose registers
are enabled (disabled).  The default is <samp class="option">-mcond-move-int</samp>.
</p>
</dd>
<dt><a id="index-mcond_002dmove_002dfloat"></a><span><code class="code">-mcond-move-float</code><a class="copiable-link" href="#index-mcond_002dmove_002dfloat"> &para;</a></span></dt>
<dt><code class="code">-mno-cond-move-float</code></dt>
<dd><p>Conditional moves for floating-point registers are enabled (disabled).
The default is <samp class="option">-mcond-move-float</samp>.
</p>
</dd>
<dt><a id="index-mmemcpy"></a><span><code class="code">-mmemcpy</code><a class="copiable-link" href="#index-mmemcpy"> &para;</a></span></dt>
<dt><code class="code">-mno-memcpy</code></dt>
<dd><p>Force (do not force) the use of <code class="code">memcpy</code> for non-trivial block moves.
The default is <samp class="option">-mno-memcpy</samp>, which allows GCC to inline most
constant-sized copies.  Setting optimization level to <samp class="option">-Os</samp> also
forces the use of <code class="code">memcpy</code>, but <samp class="option">-mno-memcpy</samp> may override this
behavior if explicitly specified, regardless of the order these options on
the command line.
</p>
</dd>
<dt><a id="index-mstrict_002dalign-1"></a><span><code class="code">-mstrict-align</code><a class="copiable-link" href="#index-mstrict_002dalign-1"> &para;</a></span></dt>
<dt><code class="code">-mno-strict-align</code></dt>
<dd><p>Avoid or allow generating memory accesses that may not be aligned on a natural
object boundary as described in the architecture specification. The default is
<samp class="option">-mno-strict-align</samp>.
</p>
</dd>
<dt><a id="index-msmall_002ddata_002dlimit"></a><span><code class="code">-msmall-data-limit=<var class="var">number</var></code><a class="copiable-link" href="#index-msmall_002ddata_002dlimit"> &para;</a></span></dt>
<dd><p>Put global and static data smaller than <var class="var">number</var> bytes into a special
section (on some targets).  The default value is 0.
</p>
</dd>
<dt><a id="index-mmax_002dinline_002dmemcpy_002dsize"></a><span><code class="code">-mmax-inline-memcpy-size=<var class="var">n</var></code><a class="copiable-link" href="#index-mmax_002dinline_002dmemcpy_002dsize"> &para;</a></span></dt>
<dd><p>Inline all block moves (such as calls to <code class="code">memcpy</code> or structure copies)
less than or equal to <var class="var">n</var> bytes.  The default value of <var class="var">n</var> is 1024.
</p>
</dd>
<dt><code class="code">-mcmodel=<var class="var">code-model</var></code></dt>
<dd><p>Set the code model to one of:
</p><dl class="table">
<dt>&lsquo;<samp class="samp">tiny-static (Not implemented yet)</samp>&rsquo;</dt>
<dt>&lsquo;<samp class="samp">tiny (Not implemented yet)</samp>&rsquo;</dt>
<dt>&lsquo;<samp class="samp">normal</samp>&rsquo;</dt>
<dd><p>The text segment must be within 128MB addressing space.  The data segment must
be within 2GB addressing space.
</p>
</dd>
<dt>&lsquo;<samp class="samp">medium</samp>&rsquo;</dt>
<dd><p>The text segment and data segment must be within 2GB addressing space.
</p>
</dd>
<dt>&lsquo;<samp class="samp">large (Not implemented yet)</samp>&rsquo;</dt>
<dt>&lsquo;<samp class="samp">extreme</samp>&rsquo;</dt>
<dd><p>This mode does not limit the size of the code segment and data segment.
The <samp class="option">-mcmodel=extreme</samp> option is incompatible with <samp class="option">-fplt</samp> and
<samp class="option">-mno-explicit-relocs</samp>.
</p></dd>
</dl>
<p>The default code model is <code class="code">normal</code>.
</p>
</dd>
<dt><a class="index-entry-id" id="index-mno_002dexplicit_002drelocs-1"></a>
<a id="index-mexplicit_002drelocs-1"></a><span><code class="code">-mexplicit-relocs</code><a class="copiable-link" href="#index-mexplicit_002drelocs-1"> &para;</a></span></dt>
<dt><code class="code">-mno-explicit-relocs</code></dt>
<dd><p>Use or do not use assembler relocation operators when dealing with symbolic
addresses.  The alternative is to use assembler macros instead, which may
limit instruction scheduling but allow linker relaxation.  The default
value for the option is determined with the assembler capability detected
during GCC build-time and the setting of <code class="code">-mrelax</code>:
<code class="code">-mexplicit-relocs</code> if the assembler supports relocation operators
but <code class="code">-mrelax</code> is not enabled, <code class="code">-mno-explicit-relocs</code> otherwise.
</p>
</dd>
<dt><a id="index-mdirect_002dextern_002daccess"></a><span><code class="code">-mdirect-extern-access</code><a class="copiable-link" href="#index-mdirect_002dextern_002daccess"> &para;</a></span></dt>
<dt><code class="code">-mno-direct-extern-access</code></dt>
<dd><p>Do not use or use GOT to access external symbols.  The default is
<samp class="option">-mno-direct-extern-access</samp>: GOT is used for external symbols with
default visibility, but not used for other external symbols.
</p>
<p>With <samp class="option">-mdirect-extern-access</samp>, GOT is not used and all external
symbols are PC-relatively addressed.  It is <strong class="strong">only</strong> suitable for
environments where no dynamic link is performed, like firmwares, OS
kernels, executables linked with <samp class="option">-static</samp> or <samp class="option">-static-pie</samp>.
<samp class="option">-mdirect-extern-access</samp> is not compatible with <samp class="option">-fPIC</samp> or
<samp class="option">-fpic</samp>.
</p>
</dd>
<dt><code class="code">-mrelax</code></dt>
<dt><code class="code">-mno-relax</code></dt>
<dd><p>Take (do not take) advantage of linker relaxations.  If
<samp class="option">-mpass-mrelax-to-as</samp> is enabled, this option is also passed to
the assembler.  The default is determined during GCC build-time by
detecting corresponding assembler support:
<samp class="option">-mrelax</samp> if the assembler supports both the <samp class="option">-mrelax</samp>
option and the conditional branch relaxation (it&rsquo;s required or the
<code class="code">.align</code> directives and conditional branch instructions in the
assembly code outputted by GCC may be rejected by the assembler because
of a relocation overflow), <samp class="option">-mno-relax</samp> otherwise.
</p>
</dd>
<dt><code class="code">-mpass-mrelax-to-as</code></dt>
<dt><code class="code">-mno-pass-mrelax-to-as</code></dt>
<dd><p>Pass (do not pass) the <samp class="option">-mrelax</samp> or <samp class="option">-mno-relax</samp> option
to the assembler.  The default is determined during GCC build-time by
detecting corresponding assembler support:
<samp class="option">-mpass-mrelax-to-as</samp> if the assembler supports the
<samp class="option">-mrelax</samp> option, <samp class="option">-mno-pass-mrelax-to-as</samp> otherwise.
This option is mostly useful for debugging, or interoperation with
assemblers different from the build-time one.
</p></dd>
</dl>

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